1. Field of the Invention
The present invention relates to implementing high-level language code on programmable chips. In one example, the present invention relates to methods and apparatus for efficiently selecting code for hardware acceleration on a programmable chip.
2. Description of Related Art
A number of benefits have spurred efforts towards developing programmable chips having both logic elements and a processor core. In one example, integrating processor cores with logic elements on a single programmable chip allows efficient and effective processing using a variety of different logic mechanisms and functions. In one example, programmable chips are provided with not only logic elements and memory, but with processor cores and other components as well. Integrating processor cores and other components onto a programmable chip allow designers to more efficiently implement descriptions on programmable devices by allowing some functions to be performed by a processor core and other functions to be performed using logic elements and hardware acceleration.
Some mechanisms for implementing a processor core entail using a general purpose programming language or high-level language. In one example, code written in a general purpose programming language such as C or C++ is converted into a hardware descriptor language (HDL) file using a tool such as the DK1 Design Suite available from Celoxica Corporation of Abingdon, England. The HDL file can then be synthesized and implemented on a programmable chip such as a programmable logic device (PLD) or a field programmable gate array (FPGA). Some available synthesis tools are Leonardo Spectrum, available from Mentor Graphics Corporation of Wilsonville, Oreg. and Synplify available from Synplicity Corporation of Sunnyvale, Calif.
However, mechanisms for efficiently optimizing code from a high level language on programmable devices are limited. It is therefore desirable to provide improved methods and apparatus for optimizing implementation of programmable chips.